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| e olet Device ) Obs w ion nt SMD le Belo r at ers e 83 V quival on" Tabt Cente c /8 E r ti ts with rma uppo o m/ lace ing Info nical S tersil.c ep R er ech ww.in "Ordt our T w (See ntac1999 SIL or October TER co IN or 81-88 (R) HA-5221/883 Low Noise, Wideband, Precision Operational Amplifier Description The HA-5221/883 is a high performance, dielectrically isolated, monolithic op amp, featuring precision DC characteristics while providing excellent AC characteristics. Designed for audio, video, and other demanding applications, noise (3.6nV/Hz at 1kHz typ), total harmonic distortion (<0.005% typ), and DC errors are kept to a minimum. The precision performance is shown by low offset voltage (0.3mV typ), low bias currents (40nA typ), low offset currents (15nA typ), and high open loop gain (128dB typ). The combination of these excellent DC characteristics with fast settling time (0.4s typ) make the HA-5221/883 ideally suited for precision signal conditioning. The unique design of the HA-5221/883 gives this device outstanding AC characteristics, including high unity gain bandwidth (40MHz typ) and high slew rate (37V/s typ), not normally associated with precision op amps. Other key specifications include high CMRR (95dB typ) and high PSRR (100dB typ). The combination of these specifications will allow the HA-5221/883 to be used in RF signal conditioning as well as video amplifiers. Features * This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Gain Bandwidth Product . . . . . . . . . . . . . .100MHz (Min) * Unity Gain Bandwidth . . . . . . . . . . . . . . . . .30MHz (Min) 40MHz (Typ) * High Slew Rate . . . . . . . . . . . . . . . . . . . . . . .25V/s (Min) 37V/s (Typ) * Low Offset Voltage . . . . . . . . . . . . . . . . . .0.75mV (Max) 0.30mV (Typ) * High Open Loop Gain . . . . . . . . . . . . . . . . . 106dB (Min) 128dB (Typ) * Low Voltage Noise (at 1kHz) . . . . . . . . .5.8nV/Hz (Max) 3.6nV/Hz (Typ) * Low Current Noise (at 1kHz) . . . . . . . . 2.0pA/Hz (Max) 1.4pA/Hz (Typ) * High Output Current . . . . . . . . . . . . . . . . . 30mA (Min) 56mA (Typ) * Low Supply Current. . . . . . . . . . . . . . . . . . . 10mA (Max) 8mA (Typ) Ordering Information OBSOLETE PART NUMBER HA4-5221/883 HA7-5221/883 SMD NO. 5962-9163401M2A 5962-9163401MPA TEMP RANGE (oC) -55 to 125 -55 to 125 PACKAGE 20 Ld CLCC 8 Ld CERDIP Applications * Precision Test Systems * Active Filtering * Small Signal Video * Accurate Signal Processing * RF Signal Conditioning Pinouts HA-5221/883 (CERDIP) TOP VIEW HA-5221/883 (CLCC) TOP VIEW +BAL -BAL NC NC NC 18 17 + 15 14 9 10 11 12 13 NC VNC NC NC 16 -BAL -IN +IN V- 1 2 3 4 + 8 7 6 5 + BAL V+ NC OUT NC -IN NC +IN NC 4 5 6 7 8 3 2 1 20 19 NC V+ NC OUT NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1 File Number 3716.1 HA-5221/883 Absolute Maximum Ratings Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VPeak Output Current (Pulsed at 1ms, 10% Duty Cycle). . . . . 100mA Continuous Output Current. . . . . . . . . . . . . . Short Circuit Protected Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC Thermal Information JC Thermal Resistance JA CerDIP Package . . . . . . . . . . . . . . . . . . . 110oC/W 27oC/W Ceramic LCC Package . . . . . . . . . . . . . . 64oC/W 13oC/W o Metal Can Package . . . . . . . . . . . . . . . . . 148 C/W 67oC/W Package Power Dissipation Limit at +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91W Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.56W Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Package Power Dissipation Derating Factor Above +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1mW/oC Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 15.6mW/oC Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8mW/oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 10V to 15V VINCM 1/2 (V+ - V-) RL 1k TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = 15V, RLOAD = 1k , VOUT = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 1 2, 3 Input Bias Current +IB VCM = 0V, +RS = 100.1k, -RS = 100 VCM = 0V, +RS = 100, -RS = 100.1k VCM = 0V, +RS = 100.1k, -RS = 100.1k V+ = +3V, V- = -27V 1 2, 3 1 2, 3 1 2, 3 1 2, 3 -CMR V+ = +27V, V- = -3V 1 2, 3 Large Signal Voltage Gain +AVOL VOUT = 0V and +10V 4 5, 6 -AVOL VOUT = 0V and -10V 4 5, 6 Common Mode Rejection Ratio +CMRR VCM = +10V, V+ = +5V, V- = -25V, VOUT = -10V VCM = -10V, V+ = +25V, V- = -5V, VOUT = +10V RL = 1k 1 2, 3 1 2, 3 4 5, 6 -V OUT RL = 1k 4 5, 6 LIMITS TEMPERATURE +25 C +125oC, -55oC o PARAMETERS Input Offset Voltage SYMBOL VIO CONDITIONS VCM = 0V MIN -0.75 -1.5 -80 MAX 0.75 1.5 80 200 80 200 50 150 -12 -12 -12.0 -11.5 UNITS mV mV nA nA nA nA nA nA V V V V dB dB dB dB dB dB dB dB V V V V +25oC +125 C, -55 C +25oC +125 C, -55 C +25oC +125oC, -55oC o o o o -200 -80 -200 -50 -150 12 12 106 -IB Input Offset Current IIO Common Mode Range +CMR +25oC +125oC, o -55oC +25 C +125 oC, -55oC +25oC +125 C, -55 C +25 C +125oC, o o o o 100 106 100 88 -55oC +25 C +125o C, -55 C o 86 88 -CMRR +25oC +125o C, -55 C o 86 12.0 11.5 - Output Voltage Swing +V OUT +25oC +125oC, -55oC +25oC +125 C, -55 C o o - 2 HA-5221/883HA-5221/883 TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = 15V, RLOAD = 1k , VOUT = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 4 5, 6 -IOUT VOUT = -10V, RL = 1k 4 5, 6 Quiescent Power Supply Current +ICC VOUT = 0V, IOUT = 0mA 1 2, 3 -ICC VOUT = 0V, IOUT = 0mA 1 2, 3 Power Supply Rejection Ratio +PSRR VSUP = 10V, V+ = +20V, V- = -15V, V+ = +10V, V- = -15V VSUP = 10V, V+ = +15V, V- = -20V, V+ = +15V, V- = -10V Note 1 1 2, 3 1 2, 3 1 2, 3 -VIOAdj Note 1 1 2, 3 NOTE: 1. Offset adjustment range is [VIO (Measured 1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. LIMITS TEMPERATURE +25oC +125o C, -55 C o o PARAMETERS Output Current SYMBOL +IOUT CONDITIONS VOUT = +10V, RL = 1k MIN 30 30 - MAX -30 -30 10 11 - UNITS mA mA mA mA mA mA mA mA dB dB dB dB mV mV mV mV +25 C +125oC, o -55oC +25 C +125 C, -55 C +25oC +125o C, -55 C o o o o -10 -11 90 86 90 86 VIO-1 VIO-1 VIO+1 +25 C +125oC, -55oC -PSRR +25oC +125oC, -55oC Offset Voltage Adjustment +VIOAdj +25oC +125oC, -55oC +25oC +125 C, -55 C o o VIO+1 TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. See AC specifications in Table 3. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = 15V, RLOAD = 1k, CLOAD = 50pF, Unless Otherwise Specified. LIMITS PARAMETERS Input Noise Voltage Density SYMBOL EN CONDITIONS RS = 0, fO = 10Hz RS = 0, fO = 100Hz RS = 0, fO = 1kHz Input Noise Current Density IN RS = 500k, fO = 10Hz RS = 500k, fO = 100Hz RS = 500k, fO = 1kHz Gain Bandwidth Product GBWP VOUT = 200mVP-P , fO = 100kHz VOUT = 200mV VOUT = 2.5V CL = 50pF NOTES 1, 5 1, 5 1, 5 1, 5 1, 5 1, 5 1 TEMPERATURE +25 C +25oC +25 C +25oC +25oC +25oC +25 C -55oC to +125oC 1 o o o o o MIN 100 90 30 MAX 24.0 8.0 5.8 11.5 6.0 2.0 - UNITS nV/Hz nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz MHz MHz MHz MHz V/s Unity Gain Bandwidth UGBW +25 C -55 C to +125 C o o o 25 25 Slew Rate SR 1 -55 C to +125 C 3 HA-5221/883HA-5221/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = 15V, RLOAD = 1k, CLOAD = 50pF, Unless Otherwise Specified. LIMITS PARAMETERS Full Power Bandwidth Minimum Closed Loop Stable Gain Rise and Fall Time Overshoot SYMBOL FPBW CLSG tR, tF OS CONDITIONS VPEAK = 10V RL = 1k, CL = 50pF VOUT = 100mV VOUT = 100mV NOTES 1, 2 1 1, 4 1 -55 Power Consumption NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2VPEAK). 3. Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.). 4. Measured between 10% and 90% points. 5. Input Noise Voltage Density and Input Noise Current Density limits are based on characterization data. PC VOUT = 0V, IOUT = 0mA 1, 3 TEMPERATURE -55oC to +125oC -55 C to +125 C +25oC +25oC oC o o MIN 398 1 - MAX 20 25 30 660 UNITS kHz V/V ns % % mW to to +125oC +125oC -55oC TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 1. PDA applies to Subgroup 1 only. SUBGROUPS (SEE TABLE 1) 1 1 (Note 1), 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6 1 4 HA-5221/883 Die Characteristics DIE DIMENSIONS: 72 x 94 x 19 mils 1 mils 1840 x 2400 x 483m 25.4m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA GLASSIVATION: Type: Nitride (Si3N4) over Silox (SIO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA WORST CASE CURRENT DENSITY: 4.2 x 104A/cm 2 SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 62 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5221/883 V+IN -IN -BAL +BAL OUT V+ 5 HA-5221 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. Typical Performance Curves Unless Otherwise Specified: TA = +25oC, VSUPPLY = 15V SUPPLY CURRENT vs TEMPERATURE TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized at: Supply Voltage = 15V, R L = 1k, C L = 50pF, Unless Otherwise Specified PARAMETERS Input Offset Voltage CONDITIONS See Table 1 TEMPERATURE +25oC Full Average Offset Voltage Drift Input Bias Current See Table 1 See Table 1 Full +25oC Full Input Offset Current See Table 1 +25oC Full Differential Input Resistance Input Noise Voltage Input Noise Voltage Density See Table 1 fO = 0.1Hz to 10Hz fO = 10Hz fO = 100Hz fO = 1kHz Input Noise Current Density fO = 10Hz fO = 100Hz fO = 1kHz THD & N Large Signal Voltage Gain See Note 1 VOUT = 0V to 10V +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC Full TYPICAL 0.3 0.35 0.5 40 70 15 30 70 0.25 10 5 3.6 7 3 1.4 0.005 128 120 UNITS mV mV V/oC nA nA nA nA k VP-P nV/Hz nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz % dB dB 6 HA-5221 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: Supply Voltage = 15V, R L = 1k, C L = 50pF, Unless Otherwise Specified PARAMETERS Common Mode Rejection Ratio Unity Gain Bandwidth CONDITIONS VCM = 10V (-3dB) TEMPERATURE Full +25oC +125oC -55oC Gain Bandwidth Product 1kHz to 400kHz +25oC +125oC -55oC Minimum Gain Stability Output Voltage Swing RL = 333 RL = 1K Full Full +25oC Full Output Current Output Resistance Full Power Bandwidth FPBW = SR/2VPEAK, VPEAK = 10V VOUT = 2.5V VOUT = 10V Full +25oC +25oC +25oC +125oC -55oC Rise Time VOUT = 100mV +25oC +125oC -55oC Overshoot VOUT = 100mV +25oC +125oC -55oC Settling Time 10VSTEP, AV = -1 0.1% 0.01% Power Supply Rejection Ratio Supply Current Minimum Supply Voltage Functional Operation Only. Other Parameters May Vary. VS = 10V to 20V +25oC +25oC Full Full +25oC TYPICAL 95 40 33 45 130 110 150 1 10 12.5 12.1 56 10 398 UNITS dB MHz MHz MHz MHz MHz MHz V/V V V V mA W kHz Slew Rate 37 37 34 13 13 15 13 13 11 0.4 1.5 100 8 5 V/s V/s V/s ns ns ns % % % s s dB mA V NOTE: 1. AVCL = 10, fO = 1kHz, VOUT = 5Vrms, R L = 600, 10Hz to 100Hz, Minimum resolution of test equipment is 0.005%. 7 HA-5221 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. PARAMETERS Input Noise Current Density CONDITIONS fO = 10Hz fO = 100Hz fO = 1kHz +25oC +25oC +25oC +25oC +25oC TEMPERATURE TYPICAL 7 3 1.4 0.005 128 UNITS pA/qHz pA/qHz pA/qHz % dB THD & N Large Signal Voltage Gain See Note 1 VOUT = 0 to 110V Full Common Mode Rejection Ratio Delta VCM = 110V (-3) Full 120 95 dB dB Unity Gain Bandwidth 8 HA-5221 Ceramic Leadless Chip Carrier Packages (CLCC) 0.010 S E H S D D3 J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 B2 B3 D D1 D2 MIN 0.060 0.050 0.022 MAX 0.100 0.088 0.028 0.072 REF 0.006 0.342 0.022 0.358 MILLIMETERS MIN 1.52 1.27 0.56 1.83 REF 0.15 8.69 0.56 9.09 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/18/94 NOTES: j x 45o B E3 E 0.200 BSC 0.100 BSC 0.342 0.358 0.358 - 5.08 BSC 2.54 BSC 9.09 9.09 8.69 h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 D3 E E1 E2 E3 e e1 h j 0.007 M E F S H S B1 0.200 BSC 0.100 BSC 0.015 0.358 - 5.08 BSC 2.54 BSC 9.09 1.27 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.91 0.08 5 5 20 1.40 1.40 2.41 0.38 0.050 BSC 0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 5 5 20 0.055 0.055 0.095 0.015 -E- L L1 e L -HL3 L2 L3 ND NE N -FE1 B3 E2 L2 B2 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. L1 e1 D1 D2 9 HA-5221 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH aaa bbb ccc M N All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 10 |
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